The present invention relates to a process of forming metal films when, for example, contact metals are formed, on a silicon semiconductor substrate and a multi layer structure.
Generally, film formation process and pattern etching process are repeated on a semiconductor substrate (hereinafter called a semiconductor wafer) of silicon to form a semiconductor integrated circuit comprising a number of circuit elements.
In this manufacturing process, materials which are low in the electric resistance and excellent in resistance to corrosion are suitable for metal wiring connecting between the circuit elements, contact metals for making electric contact with the circuit elements, and barrier metals for suppressing diffusion of Si of the substrate.
As for the materials, refractory metal materials such as Ti, W and Mo are selected. Particularly, a Ti film has excellent electrical characteristics and is resistant to corrosion and is used widely.
For example, according to a CVD (chemical vapor deposition) process using a CVD device, a Ti film is deposited by the plasma process in an atmosphere into which TiCl.sub.4 gas and H.sub.2 gas are introduced.
Here a conventional film forming process when contacts are made at elements on the semiconductor wafer surface will be described.
FIG. 10 shows a cross section of a portion which is in contact with circuit elements, for example, the sources/drains of transistors formed on the semiconductor wafer.
In the drawing, W represents a semiconductor wafer formed of, for example, a silicon substrate. A diffusion layer 3 is formed partially on a surface of the silicon substrate, and also a number of drains and sources of transistors are formed.
The drawing shows only one contact portion. An interlayer insulation film 5 made of, for example, SiO.sub.2, is formed on the surface of the semiconductor wafer W, a contact hole 7 is formed by removing the interlayer insulation film 5 over the diffusion layer 3, and wiring is connected to the diffusion layer 3 so as to make electric connection to other circuit elements.
As its typical example, a very thin Ti film 9 that is to be a contact metal is first formed on the entire semiconductor wafer surface including the interior (a wall portion) of the contact hole 7, a TiN film 11 that is to be a barrier metal, for example, is deposited on the Ti film 9, and finally a metal film 13 of tungsten or aluminum that is to be used as wiring is formed and embedded in the contact hole 7 so as to make electric connection to the diffusion layer 3.
The Ti film 9 that is to be a contact metal aims to suppress the contact resistance to the diffusion layer 3, and the TiN film 11 that is to be a barrier metal aims to suppress the mutual diffusion between the silicon component of the semiconductor wafer and the wiring metal.
When the Ti film 9 is deposited, TiCl.sub.4 gas and H.sub.2 gas are supplied as material gases, Ar gas is also supplied as gas for plasma generation, and TiCl.sub.4 gas is reduced in the presence of the plasma.
When the Ti film 9 is deposited as described above, the state of the chemical element Ti is maintained at the portion where the Ti film 9 is in contact with the chemically stable interlayer insulation film 5 since no reaction is made there, but, at the hole bottom portion where the Ti film 9 is in contact with the silicon region of the diffusion layer 3, Ti reacts with Si immediately and a TiSi.sub.2 film 15 is thereby formed, as shown in FIG. 11. This TiSi.sub.2 film 15 is about 2.5 times thicker than the Ti film 9, and its film thickness is greater along the direction of the diffusion layer 3.
In addition, the Ti film 9 cannot be prevented from corroding Si of the diffusion layer 3 side to a certain depth and absorbing Si. Due to this absorption the TiSi.sub.2 film 15 expands partially downward in a spike so as to form projections 17.
If the projections 17 break through the diffusion layer 3 and reach the semiconductor wafer at the lower side, the Ti film 9 becomes electrically conductive with the semiconductor, which causes contact leak.
Particularly, as the circuit elements are highly integrated and highly miniaturized, the diffusion layer 3 is so thinner that the frequency of occurrence of the contact leak becomes higher, which causes defectiveness and damage of articles at their manufacturing time.